1. Field of the Invention
This invention relates to the fabrication of thin film patterns on substrates. More particularly, it relates to the fabrication of metallurgy interconnection systems atop semiconductor devices.
2. Description of the Prior Art
Advances in modern semiconductor device technology have allowed increasing numbers of devices and circuits to be fabricated within a single semiconductor chip. This has required increasing microminiaturization of both the semiconductor elements as well as the interconnection metallurgy which connect the elements within the chip into circuits. Such miniaturization results in decreased costs and improved performance in integrated circuits; but it is constantly crowding the fabrication technology, particularly the photolithographic and etching techniques of the interconnection metallurgy.
In integrated circuit logic and memory design, for example many thousands of impurity regions are conventionally fabricated in a silicon chip approximately 125-200 mils square. Such regions form transistors, diodes, resistors and the like which are then connected together by the metallurgical patterns atop the chip to form various circuits and for connection to input-output terminals.
This interconnection metallurgy system atop the chip is extremely complex and usually employs two or three separate levels of complex thin film conductor patterns, each separated by one or more layers of dielectric material. Ordinarily, the first level conductive pattern on the chip surface interconnects the transistors, resistors, diodes, etc. into circuits and also provides for circuit-to-circuit connections. The latter function is usually provided by parallel conductive lines connected to the individual circuits. The second level conductive pattern conventionally completes the circuit-to-circuit connection and makes contact to I/O terminals which are connectable to a support such as a module, substrate or card. The second level usually consists of parallel lines that are transverse to the aforementioned parallel lines of the underlying first level conductive pattern. In advanced designs third, and even fourth, levels may be required for power and I/O connections.
The area occupied within the semiconductor chip by the impurity regions which make up the active and passive semiconductor devices actually occupies substantially less than the total available chip area. The support area required by the metallurgy is the limiting factor in determining the number of circuits which can be utilized on a chip.
At the present state of technology, the lower limits of the width of an interconnection metallurgy stripe are usually thought to be imposed primarily by photolithographic technology. The line widths are in the order of 0.15 mils with a separation on the order of 0.15 mils for long lines. However, a more severe restriction exists when conventional techniques are used to form multi-level conductive patterns.
At present it is necessary to etch the dielectric layers to form feedthrough patterns from one level to another. The standard process of interconnecting one level of metallurgy to another involves depositing an insulator such as SiO.sub.2 atop a first level metallurgical pattern disposed on a substrate. The glass is typically deposited pyrolytically, although the sputtered glass position process described in U.S. Pat. No. 3,983,022 of Auyang et al, is more advantageous. Said patent is assigned to the same assignee as the present application.
A photo-resist layer is then deposited, exposed and developed so that the via hole pattern is formed in the photoresist over the glass. The exposed glass portions are then etched to form the via holes down to the first level metallurgy. A second level metallurgical pattern is then deposited atop the remaining glass layer and into the via holes for connection to the first level pattern.
A critical step in the process involves the alignment of the photoresist mask with the first level pattern. Misalignment of the mask may result in etching the insulative substrate beneath the glass layer, commonly termed overetching. In addition, overetching may result in the removal of the glass between conductive stripes in the metallurgical pattern. To compensate for such contingencies, it is common to provide increased areas of metallurgy, termed pads, at via hole sites. These pads do effectively prevent overetching; but they also substantially increase the chip area required for interconnection metallurgy.
It is ordinarily necessary to provide for the possibility of locating two via holes in adjacent parallel lines in side-by-side relation on the substrate. Photolithographic and masking technology requires that the diameter of a via hole at the top of the dielectric or insulating surface be at least 0.25 mils. A conventional pad which interconnects levels of metallurgy must be wider than (overlap) the via hole by at least 0.40 mils or else a sharp-pointed, upperly-extended lip occurs about the via hole which is detrimental to mask life. It is also difficult to deposit a layer of metal or glass over the pad. This requires that the pads have a diameter of 0.65 mils. Because adjacent pads must be located at least 0.2 mils apart, the minimum center-to-center spacing between two parallel, adjacent conductive stripes is of the order of 0.85 mils. In an ideal structure, i.e., one which did not require pads over the via holes, the stripes could be spaced a at 0.45 mils center-to-center distance. In addition, the via connections could be as wide, or slightly wider than, the conductive stripe to which they are connected. This is termed a "zero-overlap" via.
One solution to these problems is found in U.S. Pat. No. 3,844,831 issued in the names of E. E. Cass et al., and assigned to the same assignee as the present invention. The Cass et al. technique involves the use of dielectric layers of dissimilar etching characteristics, whereby an etchant which attacks one type of dielectric does not substantially affect the other. Although the Cass et al. invention has been successful, it involves more fabrication steps and more complicated processing than the standard process.
Another method for forming via holes, described in U.S. Pat. No. 3,804,738 by Lechaton et al, involves planarizing the insulation disposed over narrow conductive stripes by sputtering, followed by etching the via holes in the planarized insulator down to the stripes. Although effective in reducing reliability problems, the Lechaton et al planarization process is time-consuming; in addition, some degree of overetching is ordinarily required to compensate for mask misalignment.